Consider a 5 staged pipelined MIPS processor where its operation is divided into 5 stages. Each stage is timed as shown below. What is the clock period of this processor. Execution Time Stage: Fetch Decode Execute Memory Write Back Time: 180 ns 102 ns 241 ns 313ns 50 ns a 886.00 ns O b. 177.20 ns O c. 50.00 ns O d. 313.00 ns O e. None of the options