Consider a byte addressable MIPS processor $($discussed in the textbook$)$ has a $32-$bit address bus and a cache memory consists of $256(=28)$ sets. Assume that a one$-$way set associated $($also known as direct mapped$)$ cache is used to implement cache with a block size of $4$ main memory words.

A memory read request $($e$.$g$.,$ lw$)$ from a main memory location of $0$xCCCCCCCC is being executed. The memory read request will first go to cache memory. The cache address mapping hardware will decompose the main memory address $0$xCCCCCCCC into byte$-$offset, block$-$offset, set, and tag fields. Determine the following fields for this address decomposition: