Consider a direct-mapped data cache that can accommodate 256KB of data with eight 4byte words per block and that uses a 32-bit address. (a) How many bits are used for the block offset? For word offset? (b) How many bits are used for the index? (c) How many bits are used for the tag? (d) Provide the design of this cache and the address format, similar as on Slides I19, including gates, multiplexers and comparators where needed. (e) Assuming that CPU generates address 0XABCDE678 and it is a hit, - what is the cache entry accessed? - provide as much as possible of contents for that entry.