Consider a MIPs machine with a 5-stage pipeline with a cycle time of 10ns. Assume that you are executing a program where a fraction f of all instructions immediately follow a load upon which they are dependent. Also, there is no other data hazard or control hazard With forwarding enabled, what is the total execution time for N instructions (in terms of)? Consider a scenario where the MEM stage, along with its pipeline registers, needs 12ns There are now two options: add another MEM stage so that there are MEMI and MEM2 stages or increase the cycle time to 12ns so that the MEM stage fits within the new cycle time and the number of pipeline stages remain unaffected. For a program mix with the above characteristics, when is the first option better than the second. Your answer should be based on the value off. (You may ignore the first few cycles to fill the pipeline.) Embedded processors have two different memory regions a faster scratchpad memory and a slower normal memory. Assume that in the 6-stage machine (with MEM1 and MEM2 stages), there is a region of memory that is faster and for which the correct value is obtained at the end of the MEM1 stage itself while the rest of the memory needs both MEMI and MEM2 stages. For the sake of simplicity, assume that there are two load instructions lw fast and lw.slow that indicate which memory region is accessed. If 40% of the fraction f mentioned above get their value from the fast memory, how does the answer to the previous question change