Consider a paged logical address space $($composed

of $32$ pages of $2$ Kbytes each$)$ mapped into a $1-$

Mbyte physical memory space.

a$.$ What is the format of the processor$$s logical

address?

b$.$ What is the length and width of the page table

$($disregarding the $$access rights$$ bits$)?$

c$.$ What is the effect on the page table if the physical

memory space is reduced by half? into a single