Consider a processor and a program that would have an IPC of 1 with a perfect 1-cycle L1 cache. Assume that each additional cycle for cache/memory access causes program execution time to increase by one cycle. Assume the following MPKIs(Misses per Kilo instructions) and latencies for the following caches:

• L1: 32 KB: 1-cycle: 60 MPKI
• L2: 256 KB: 10-cycle: 50 MPKI
• L3: 2 MB: 30-cycle: 20 MPKI
• L4: 32 MB: 100-cycle: 5 MPKI
• Memory: 250-cycles

Assume the program has 1000 instructions. Please estimate the program execution times for the following cache configurations:

1. L1-L2
2. L1-L2-L3
3. L1-L2-L3-L4

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