Consider a simple 5 stage (FET/DEC/OpF/EXE/WB) pipeline design with no branch prediction. For a taken branch, conditional or unconditional, the PC is updated during the WB stage, allowing the FET stage to start during that same phase.

What is the speed up achieved by adding a branch predictor and branch target buffer?

Assume a base CPI of 1.5, 15% of the instructions are conditional branches, each taken 60% of the time and 5% of the instructions are unconditional branches.

Also assume that the branch predictor is correct 90% of the time and 80% of the branches are found in the branch target buffer. If the branch is correctly predicted as taken and is in the branch target buffer, there is a 1 cycle branch penalty. If the branch is correctly predicted as not taken, there is no branch penalty. If a not-taken branch is incorrectly predicted as taken or if a not-taken branch is incorrectly predicted as taken AND is in the branch target buffer, the correct next instruction will be fetched during the EXE phase of the branch instruction processing. If the branch is taken and the branch is NOT in the branch target buffer, the next instruction will be fetched during the WB phase of the branch instruction, regardless of the prediction.