Consider a three-bit analogue to digital converter (ADC) (as illustrated below) for the case of a sinusoidal input (as an example). Here any sample is quantised by rounding either up or down. That is, any sample ((nT) is quantised x nT to the nearest quantisation level before being outputted as a three bit code). The units on the y-axis are in volts ) What is the dynamic range (o volts) of the input analogue signal (()) for the N-3-bit ADC in the figure? (i) Suggest an appropriate Gray Code for the ADC in the figure below. That is, instead of labelling the eight What is the quantisation interval in volts? quantisation levels 000,001, 010,011,10011 as shown, try a different order so that any adjacent code is only one bit different from those adjacent to it. Why is this useful at the DAC if there are bit errors during transmission? (Assume that a single bit error for a three bit code is more likely than 2 or 3 bit errors). (iii) Calculate the quantisation noise power, P = E e2 (n7) = , where e(n7)= x (nT) 12 -(,)-Then calculate 0 the signal-to-noise ratio (SNR(dB)) at the output of the ADC (for the sinusoidal signal shown in the figure). What is the minimum value for N(bits per sample in the ADC) to achieve greater than 30dB (SNR(dB)). (iv Give the names of three different ADC technologies. What are the fastest sampling rates? (v) Assume that we have two ADCs sampling at F Hz each. How can we configure these two to have arn effective sampling rate of 2F, Hz? How can we generalise to M ADCs-sketch the setup. 1kHZ SINUSOID SAMPLED AT Fs = 25 kHz , 3-BIT QUANTISER 1.5 true samples of continuous-time waveform RED quantised samples of continuous-time waveform 110 101 100 011 010 001 0.51. -0.5 -1 8 (N=3bits/sample) QUANTISATION LEVELS FOR ADC 1.5 0 0.1 0.2 03 0.4 05 06 0.7 0.8 0.9 1 TIME IN MSECS