Consider a 512x256 ?SRAM bank (512 ?rows and 256 ?columns). ?Bit lines are pre-charged to VDD = 2.5 ?V before each read operation. A read operation is complete when the bit line has discharged by 0.36 ?V. ?A memory cell can provide an average of 0.6 ?mA of pull-down current to discharge the bit line. Assume the word line resistance is 40 ?ohms per memory cell, the word line capacitance is 12fF per memory cell, and the bit line capacitance is 4 ?fF per cell. Ignore the bit-line resistance.

(a) ?Calculate the row delay (i.e., ?word line charging time) ?for this memory array by using the Elmore delay model. Calculate the column delay (i.e., ?bit line discharging time) ?for this memory array by using the average current method. Finally, calculate the access delay (i.e., ?row delay + ?column delay) ?for this memory array.

(b) ?Reorganize this memory array (i.e., ?change the number of rows and columns and keep the same SRAM capacity) ?so that the total access delay is minimized. What is this minimum access delay? You are not required to generate a result. Show your

calculations with explanations.