Consider an in-order pipeline that has the following stages. Unlike our 5-stage pipeline, a register read takes an entire cycle and a register write takes an entire cycle (not a half cycle).

Fetch	Decode	Regread	IntALU	Regwrite
			IntALU	Datamem	Datamem	Regwrite

After instruction fetch, the instruction goes through a separate Decode stage where dependences are analyzed, then a separate Regread stage where input operands are read from the register file. After this, an instruction takes one of two possible paths. Int-adds go through the stages labeled "IntALU" and "Regwrite". Loads/stores go through the stages labeled "IntALU", "Datamem", "Datamem", and "Regwrite", i.e., it takes two cycles to retrieve data from the data memory unit. How many stall cycles are introduced between the following pairs of successive instructions (i) for a processor with no register bypassing and (ii) for a processor with full bypassing? (40 points)

add $1, $2, $3 add $4, $1, $5

lw $1, 8($2) lw $3, 8($1)