Consider an N-input NOR gate with an on-resistance 1/4th that of a NOR gate with unit n- type transistors. Following along as the book does for an N-input NAND gate compute each of the following as a function of N? Justify as necessary. (You may get slightly different answers for N even or N odd)

(a) Draw a stick figure (you may have to have different figures for N even or odd) and use those figures for the following

(b) What are the widths of the transistors

(c) What is the input capacitance

(d) What is the output diffusion capacitance

(e) What is the parasitic delay

(f) What is the logical effort

(g) What is the effort delay

(h) What is the drive?

(i) For h=10 and a 65nm technology, what is the delay thru your NOR in pico seconds.

oOO R R R R Inc Inc Inc 3nC nC FIGURE 4.23 n-input NAND gate parasitic delay oOO R R R R Inc Inc Inc 3nC nC FIGURE 4.23 n-input NAND gate parasitic delay