Consider an SRAM device with address range $0$x$5$C$00$ to $0$x$5$FFF$.$a$.$ Design a memory address decoder for this SRAM device using only maximum $4-$inputAND$/$NAND gatesb. How many address lines are required for the SRAM?c$.$ Find the capacity of the SRAM.d$.$ Draw a block diagram of the SRAM interfaced with a CPU having $16$ address lines and $8$data lines. Also show where the memory address decoder fits in the diagram. Show allpower pins, address pins, data pins, and control pins, and label all input and output pins clearly