Consider an Unpipelined processor where it takes 36ns to go through the circuits and 0.5s for the latch overhead.

Assume that the point of production and consumption in the unpipelined processor are separated by 12ns. assume that 1/2 the instructions do not produce a data hazard and 1/2 depend on the preceding instruction.

i) What is the maximum throughput of the unpipelined architechure for the processor in instructions per second (IPS) ii) We build a 12-stage pipelined architechure. Please compute the percentages of increase/decrease in throughput for the pipelined architechure compared to unpipelined process