Consider RISC pipeline with five stages IF, ID, EX, MEM, and WB. Assume that four numbers a, b, c, and d are saved at memory addresses 1000, 1100, 1200, and 1300, respectively. Compute (a + b)*(c - d) with the following instructions: Lw R1, 1000//Fetch a from memory address 1000 Lw R2, 1100//Fetch b from memory address 1100 Add R3, R2, R1//a + b is saved in register R3 Lw R4, 1200//Load c from the memory address 1200 Lw R5, 1300//Load d from the memory address 1200 Sub R6, R4, R5//Compute c-d R7, R3, R6//compute (a + b)*(c - d) a) What hazards does the program have? b) Point out stalls in the pipeline c) Calculate the total number of cycles. d) Rearrange the instructions to remove as many stalls as possible