Consider the AMD Opteron virtual memory system, the page tables for which are depicted below. Note that the architecture supports 64 bit virtual addresses but in most implementations so far the most significant 16 bits are constrained to be all Os or all 1s. The page tables have four levels of hierarchy. Recall that the Opteron has separate L1 instruction and data TLBs, each is fully associative and has 40 entries. These are backed by separate L2 instruction and data TLBs, each of which is four-way set associative with 512 entries (128 sets x 4 ways).