Consider the circuit and timing parameters below CLK CLK YM MD ccq-20 ps pcq30 ps _setup 10 ps t hold30 ps t_pd (per gate)15 ps t-cd (per gate) -10 ps Assume the clock runs at 4 GHz. How much clock skew can this circuit tolerate? Select one: O a. 165 ps O b. 30 ps O C. None O d. 185 ps