Consider the circuit shown in thesitive edge triggered flipfigure below which consists ofa poflop with selective load capability$($identified as MICK$)$ and a level sensitive D$-$type latch$($labelled as KEITH$).$ There is aninput bus$($consisting of a single wire$),$an output bus, and twoing diagram which is included at thtri$-$state buffers.e end of this question.Complete the tinIndicate in the provided timing diagram the behavior of the output ofthe flip$-$flop and the latch$($q mick and g keith$)$ as well as t$!$he behavior of the output bus between the indicated $\text{'}$start$$ and$$end$$ times. Use the symbol$$Z$$when it is in the high.to denote the state of the output busgiven diagram, it is assumed that timpedancehe initial value ofg mick is$($tri$-$state value$).$ In that the timing diagramofg keith is logic $\text{'}1.$ Note also th:logic $\text{'}0$ and that the initial values the nature ofthis designintentionally contains a fatal design error. You are to explain in word