Consider the code segment in RISC-V which is similar to LEGv8 f0, 0(x0)load fO from address 0+x0 fld fild f2, 0(x2) load f2 from address 0+x2 fmult f2, 12, fo ;f2-12-10 fsd addwi x2,x2, 8 X2 x2+8 subwi x4, x3, x2 ;x4 = x3-x2 bne x4, x0, loop branch to loop if x4!- 0 loop: f2, 0(x2) store x2 at address 0+x2 Assume the initial value of x3 is x2 +64. Assume x0-0 and x2-16, and the memory contains: 9.0 4.0 1.0 7.0 0 8 16 24 5.0 3.0 32 40 1.0 48 2.0 56 64 8.0 7.0 72 5.0 80 The cache size is 64 bytes and the block size is 16 bytes. Make a table similar with Example 5 in Lecture sl a) Display the content of memory, cache hit or miss status, and the content of cache as the loo executes, assuming the cache is direct mapped, with write through and no write allocate. b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and write back, and write allocate. Consider the code segment in RISC-V which is similar to LEGv8 f0, 0(x0)load fO from address 0+x0 fld fild f2, 0(x2) load f2 from address 0+x2 fmult f2, 12, fo ;f2-12-10 fsd addwi x2,x2, 8 X2 x2+8 subwi x4, x3, x2 ;x4 = x3-x2 bne x4, x0, loop branch to loop if x4!- 0 loop: f2, 0(x2) store x2 at address 0+x2 Assume the initial value of x3 is x2 +64. Assume x0-0 and x2-16, and the memory contains: 9.0 4.0 1.0 7.0 0 8 16 24 5.0 3.0 32 40 1.0 48 2.0 56 64 8.0 7.0 72 5.0 80 The cache size is 64 bytes and the block size is 16 bytes. Make a table similar with Example 5 in Lecture sl a) Display the content of memory, cache hit or miss status, and the content of cache as the loo executes, assuming the cache is direct mapped, with write through and no write allocate. b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and write back, and write allocate