Consider the data path of a CPU on the right. With this configuration a register-to-register operation (e.g. C=A+B) takes 3 clock cycles; i.e. a fixed amount of time regardless of the complexity of the ALU operation. In the first cycle data is loaded into the ALU input registers from the main registers. For all registers the loading operation takes a maximum of 4 ns (nanoseconds). The ALU can compute any one of the 6 types of operations at a time. These take 5, 12, 8 12, 3, 11 ns each to produce the result at the output of the ALU. At the end of the ALU operation the data will be ready and in the second cycle the data is written into the ALU output register. Note that in this architecture every ALU operation needs to be completed in a single clock cycle. In the third cycle the value in the output register is written back to the destination (main) register(s).

a) Find the maximum clock frequency and bandwidth in MIPS that this microprocessor can handle for repetitive register-to-register operations if all operations are performed without any overlap between instructions (assume no wait time for fetching instructions). Note that the clock frequency will remain constant once set for operation and the cycle time will be the same for all clock cycles.

b) Repeat part (a) if the data path operates in a pipelined fashion, i.e. all units are kept busy. In any given cycle, the input, output and the destination registers are being loaded, and the ALU is performing an operation for the corresponding instruction. Assume there are no register read/write conflicts and instructions can be executed in order with a new instruction starting every clock cycle.

c) Find the program completion time of a 500,000 instruction program separately for parts (a) and (b). Assume the instructions are readily available in IR and no extra time is spent to fetch them from memory.

Register B ALU input register ALU input bus ALU ALU Output register Register B ALU input register ALU input bus ALU ALU Output register