Consider the execution of the following sequence of four instructions on a five$-$stage pipelined processor which uses the always$-$not$-$taken strategy for branch prediction and has both the forwarding unit and hazard detection unit.

add x$12,$ x$6,$ x$5$

sub x$10,$ x$11,$ x$12$

beq x$11,$ x$12,$ LABEL

sd x$11,0($x$12)$

Suppose the third instruction is detected to have an invalid target address and cause an exception in the ID stage. Fill in the following table by showing what instructions are in the IF$,$ ID$,$ EX$,$ MEM and WB stages. Note that each instruction in your answer should be one chosen from the given four instructions, the NOP instruction $($or bubble$),$ and the first instruction of the exception $\backslash$table$[[,$IF$,$ID$,$EX$,$MEM,WB$],[$Cycle $1,,-,-,-,-],[$Cycle $2,,,-,-,-],[$Cycle $3,,,,-,-],[$Cycle $4,,,,,-],[$Cycle $5,,,,,]]$handler