Consider the figure above and the delays in ns given in the table below,

Unit

Delay $($ns$)$

PC

$0\mathrm{.}5$

Inst Mem

$2$

RegDst Mux

$0\mathrm{.}1$

Reg File read

$1$

ALUSrc Mux

$0\mathrm{.}1$

ALU

$1$

Data Mem

$2$

Memtoreg Mux

$0\mathrm{.}1$

Reg File write

$1$

Branch Adder

$1$

Branch Mux

$0\mathrm{.}1$

PCSrc Mux

$0\mathrm{.}1$