Consider the following algorithm z=max(a2+b2,4ab). a) Derive dataflow diagram. b) Derive the ASMD chart for the schedule. Assume that one arithmetic unit is used and that unit can perform any operation. c) You need to process input stream of 1000 data points a and b that arrive at the maximum speed that your design supports. How many clock cycles does it take to execute 1000 data points based on ASMD in b)? d) Implement this circuit as a pipeline circuit so that the clock period that you can achieve is smaller than 25ns. Show where you would add pipelined registers so that the number of pipeline stages is minimal. Assume the following delays of the components: mul: 19ns,max:8ns, add/sub 11ns,Tcq=0.5ns and Tsetup =0.5ns. What is the minimum clock period? e) You need to process input stream of 1000 data points a and b that arrive at the maximum speed that your design supports. How many clock cycles does it take to execute 1000 data points based on pipelined design in d)? Question 4B (total 20 points) Find a hazard-free minimum-cost POS implementation of the function: f(x1,,x4)=M(0,2,3,7,10)+D(5,13,15)