Consider the following assembly code: Instruction Description LOAD RIMI Read data from memory address MI and store in RI LOAD R2, M2 Read data from memory address M2 and store in R2. OR R5, R1, R2 JUMP Target1 Target2: XOR R2, R1, RI Logical Ex-OR between contents of Rl with Rl and store result in R2 Target3: ADD R7, R1, R5 Add contents of Rl and R5 and store to R7 OR R2, R4, R6 Logical OR between contents of R4 with R6 and store result in R2 OR R5, R3, R7 ADD RS, R7, R3 AND RI, R2, R3 Target: SUB R3, R1, R2 Subtract content of R2 from Rl and save result in R3; here R1 = R2 BNEZ R3, Target2 Jump to Target2 if R3 is non-Zero BEZ R3, Target3 Jump to Target3 if R3 is Zero OR R2, R4, R6 Logical Or between contents of R4 with R6 and store result in R2 STORE M4, R2 Save contents of R2 to memory address M4 END Use five-stage pipeline containing Fetch Decode. Memory read, Execute. Write-back units, show the execution of program (at least 20 time steps). Data dependencies and control hazards, i detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 1 2 3 4 5 LOAD RIMI LOAD R2, M2 OR RS, RI, R2 JUMP Target! Target2: XOR R2.RI. Ri Target3: ADD R7, R1 R5 OR R2 R4, R6 OR R5, R3, R7 ADD RS, R7, RS AND RI, R2, R3 Targeti: SUB R3, R1, R2 BNEZ R3, Targe 2 BEZ R3, Targets OR R2, R4, R6 STORE M4, R2 END