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Consider the following change to the interrupt mechanism discussed in class. Suppose we are not concerned with protection issuesusers are well behaved and they dont
Consider the following change to the interrupt mechanism discussed in class.
Suppose we are not concerned with protection issuesusers are well behaved and they dont use priviledged instructions and stay within their memory area.
Suppose now the mode bit is always 1, even in user program execution, since protection is not an issue.
when an interrupt occurs, hardware saves only the PC, not the PSW. Similarly, hardware loads from the Interrupt vector only the PC, not the PSW. RTI instruction reloads only the PC, not the PSW.
Any problems with this scheme?
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Database Management An Organizational Perspective
Authors: Richard T. Watson
1st Edition
0471305340, 978-0471305347
