Consider the following circuit where the combinational circuit is represented by COMB and clock skew is represented by t_skew. Given the following parameters: FF setup time = 20ns FF hold time = 10ns FF propagation delay = 5 to10ns Tcomb1 = 5ns to 7ns Tcomb 2 = 6ns to 11ns (a) What is the minimum clock period with t_ skew1 = t_skew2 = 0? (b) Now set Tcomb1 = 1 to 4ns. Is there a setup time violation for the middle flip-flop? If no, what is the setup time margin? (c) Now set Tcomb1 = 1 to 4ns. Is there a setup time violation for the middle flip-flop? If no, what is the setup time margin? (d) What are the minimum values of t_skew1 and t_skew2 that will fix the violations (e) What is the minimum clock period after violations have been fixed