Consider the following circuit: Wire D 00 D Q teno Wire A cin cout 00 D Q Leno cin + Cout Wire B + Wire C Wire E 4 Assume the following: The not gate has a delay of 1 ns. The adder block has a delay of 10 ns. The multiplier block has a delay of 15 ns. The registers have clk-to-q delays of 2 ns each, a setup time of 5 ns, and have the same hold time. .