Consider the following code segment, where the branch is taken 30% of the time and not-taken 70% of the time.

R1 = R2 + R3 R4 = R5 + R6 R7 = R8 + R9 if R10 = 0, branch to linex R11 = R12 + R13 R14 = R11 + R15 R16 = R14 + R17 ... linex: R18 = R19 + R20 R21 = R18 + R22 R23 = R18 + R21 ...

Consider a 10-stage in-order processor, where the instruction is fetched in the first stage, and the branch outcome is known after three stages. Estimate the average CPI of the processor under the following scenarios (assume that all stalls in the processor are branch-related and branches account for 15% of all executed instructions):

1.On every branch, fetch is stalled until the branch outcome is known.

2.Every branch is predicted not-taken and the mis-fetched instructions are squashed if the branch is taken.

3.The processor has two delay slots and the two instructions following the branch are always fetched and executed, and

1.You are unable to find any instructions to fill the delay slots.

2.You are able to move two instructions before the branch into the delay slots.

3.You are able to move one (note: one, not two!) instruction after label "linex" into one of the delay slots.

4.You are able to move two instructions immediately after the branch (in the original code) into the delay slots.