Consider the following code sequence. Assume Direct mapped cache.

STR R$3,256($R$0)$

LDR R$1,2048($ R$0)$

LDR R$2,256($R$0)$

Write$-$through cache maps $256$ and $2048$ to the same block. A four words write

buffer is not checked on a read miss. Will the value in register R$2$ always be equal

to the value in register R$3$ or R$2?$ Discuss.