Consider the following combinational circuit that has four inputs A, B, C, D, and one output Z The delay of the inverter is 1 ns the delay of the 2-input OR, AND, NOR and NAND is 2 ns and the delay of the 3-input OR is 3 ns. A w3 B w2 W4 Z A w5 D a) (5 points) Write a gate-level description in Verilog using the provided gate delays. b) (3 points) Write a second description in Verilog using one continuous assign statement and one expression for Z with delay along the critical path. Do NOT simplify expression