Consider the following computation loop Xi+1 = aXi by which is the inner loop in a numerical algorithmic process. For numerical convergence, this loop is supposed to run for a large number of iterations. The constants a and b are initialized in float registers. Loop: LD MULTF LD MULTF SUBF SD SUBI SUBI BNEQZ FO,0 (R1) FO, FO, F2 F4,0 (R2) F4, F4, F6 FO, FO, F4 0 (R1), FO R1, R1,8 R2, R2,8 R1, Loop - WRITE Instruction FP ALU OP FP ALU OP Load double Load double // Load // Multiply // Load // Multiply // Subtract // Store // Decrement // Decrement // Branch not equal Assume the pipeline data dependent latencies between instructions (WRITE to READ operands) are given by the following Table. For example, LD FO,0 (R1) and MULTF FO,FO,F2 have a RAW dependency with latency (load slot) 1 slot. Also, the machine uses float arithmetic units (ADDF and MULTF) which are pipelined and embedded in the instruction pipeline. You may consider 4-stage float pipes. Furthermore, delayed branching is available. READ Instruction 1 Another FP ALU OP store double FP ALU OP Store double Latency in Cycles 3 2 1 0 a) Unroll the above loop as many times as necessary to schedule it without any delays, collapsing the loop overhead instructions. b) Briefly show the scheduling of the entire loop iterations. c) Comment if there are other unrollings feasible.