Consider the following data-path:

With this single-cycle processor, you can only execute a limited number of instructions. Now, we want to extend the processor to also execute bne (Branch not equal). To support this, we want to add a new signal, bne, and change the existing branch signal to beq (as the existing branch signal actually conducts beq operation). We do not want to redesign the existing ALU for this. Instead, we want to add logic gates directly to the above data-path to support bne. The format of bne is as follows:

bne Rs, Rt, offset

a. What kind of functional blocks (if any) do we need for this instruction? Explain (or draw) what gates need to be newly added and how new bne and existing signals will be used to implement bne.

b. Show what values should be set to the control signals to execute bne. The control signals that you need to show include the new bne, beq signals, and the existing seven signals (RegDst, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, and RegWrite).

25-0] Shift Left 2 4 [31-26] PC +4 [31-28] + S Sum Shift Left 2 [25-21Read CLK Reg. 1 # Read Reg. 2 # Write Reg # Write Data Register File 20-16] PC Addr Data Read data 1 15-11] Zero Res Addr Read data 2 I-Cache /I-MEM 0 Read Data Write Data RegWrite [15-0] egDst ranc Sign Extend ALU contro D-Cache l 32 D-Mem ALUSrc ControlALUOp MemtoReg MemRead Jump 25-0] Shift Left 2 4 [31-26] PC +4 [31-28] + S Sum Shift Left 2 [25-21Read CLK Reg. 1 # Read Reg. 2 # Write Reg # Write Data Register File 20-16] PC Addr Data Read data 1 15-11] Zero Res Addr Read data 2 I-Cache /I-MEM 0 Read Data Write Data RegWrite [15-0] egDst ranc Sign Extend ALU contro D-Cache l 32 D-Mem ALUSrc ControlALUOp MemtoReg MemRead Jump