Consider the following DLX code. Assume that initial values of all registers and memory are zero. In this part assume there IS forwarding hardware. Assume the architecture shown at the end of this problem (registers are written in the first half of the cycle and read in the second half of the cycle and that branches are resolved during decode).

Fill in the pipeline timing diagram at the bottom showing the execution of the DLX code given below. Use the following codes: F = fetch, D = decode, X = execute, M = memory access, W write back, s = stall. The first instruction is filled in for you. Show only the first ten instructions executed. List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction: Instr. No. Instruction Write back cycle 4 addi add beqz sub lw begz sub add S w sub r1,r0,#3 r2,rl,r3 r2,L1 r7,r2,r3 r5, 13 (r2) r5.L2 r7,r3,r8 rl,r2,r7 9 (r2),rl r3,r2,r1 L1 : L2: (10) instruction 0 2 345 67 8 9 10 11 12 13 14 15 16 1718 19 instruction 20 21 22 2324 25 2627 28 29 30 31 32 33 3435 |36 3738 39