Consider the following instruction breakdown that decomposes an instruction into $4$ parts:

OPCODE DST SRC IMM

OPCODE specifies the OPeration's CODE.

DST specifies a DeSTination register.

SRC specifies a SouRCe register.

IMM specifies a $2\text{'}$s complement value $($that$\text{'}$s IMMediately available as part of the instruction$).$

Assume the architecture has $24-$bit instructions, $61$ opcodes, and $16$ registers.

A$.)$ What is the minimum number of bits required to represent an OPCODE?

$7$

B$.)$ What is the minimum number of bits required to represent a register?

$5$

C$.)$ What is the maximum number of bits that can be used to represent the IMM value?

$5$

D$.)$ What is the largest positive value in base $10$ that can be represented by the IMM value?

$16$