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Consider the following instruction sequence executing on a 5 - stage ARM pipeline with static branch prediction and branches are resolved early in the execute

Consider the following instruction sequence executing on a 5-stage ARM pipeline with
static branch prediction and branches are resolved early in the execute stage. The
instruction sequence shown results in control hazards. (Note that the loop counter in R0
is set to 2.) Suppose the CPU uses a static branch prediction policy of predict-always-
untaken. How many cycles are wasted due to control hazards? Assume the program
executes several more non-branch instructions after the label DONE.
a.0
b.2
c.4
d.8
e.12
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