Consider the following instruction set for a hypothetical computer that can address only 64 memory locations. The machine has an 8-bit accumulator register named AC. In the following table a refers to a 6-bit memory address. Similar to VSCPU, it has registers IR, DR, AR & PC. Instruction STAC a INCM a ADD a CLAC Instruction Code 00 a 01 a 10 a 11 - Operation MEM[a] AC MEMO MEMO) + 1 AC AC + MEM[a] ACO (a) Show a complete RTL specification of a design for this ISA. Hint: CLAC needs one state, ADD & STAC need 2 states each & INCM needs 3 states. Fetch phase takes 3 states. NOTE: No need to draw the state diagram! (6) Show the state assignment for all the states assuming a hard-wired control unit that uses a five-bit counter with a parallel input based on an IR map of 1 SIR> 00. Consider the following instruction set for a hypothetical computer that can address only 64 memory locations. The machine has an 8-bit accumulator register named AC. In the following table a refers to a 6-bit memory address. Similar to VSCPU, it has registers IR, DR, AR & PC. Instruction STAC a INCM a ADD a CLAC Instruction Code 00 a 01 a 10 a 11 - Operation MEM[a] AC MEMO MEMO) + 1 AC AC + MEM[a] ACO (a) Show a complete RTL specification of a design for this ISA. Hint: CLAC needs one state, ADD & STAC need 2 states each & INCM needs 3 states. Fetch phase takes 3 states. NOTE: No need to draw the state diagram! (6) Show the state assignment for all the states assuming a hard-wired control unit that uses a five-bit counter with a parallel input based on an IR map of 1 SIR> 00