Consider the following logic function: f=ABC+BC.D+EFA+F.BG+C.H a) Assuming a programmable device with an unlimited number of 8-input / 1-output look-up-tables, show how the function would be implemented on the device. For the content of the LUT, you may only show the addresses that will be set to one (no need to show the entire table or the multiplexers). b) Repeat part (a) assuming that the programmable device contains an unlimited number of 4-input / 1-output LUTs. c) Repeat part (a) assuming that the programmable device contains an unlimited number of 2-input / 1-output LUTs. d) For parts (a) through (c), assuming that in all the cases, each LUT has a delay of X time units and that the interconnect has zero delay, compute the delay of the overall design for each case. For parts (a) through (c), make sure you use the least number of LUTs in each case