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Consider the following sequence of instructions. 1 addi s 2 , s 2 , 1 2 add s 6 , s 1 , s 3

Consider the following sequence of instructions.
1 addi s2,s2,1
2 add s6,s1,s3
3 add s1,s2,s3
4lws5,o(s1)
5lwt1,o(s5)
(a) Determine the clock cycle at which each of the instructions in the sequence given above
would be completed, assuming the 5-stage pipeline without forwarding as covered in
class, and numbering the clock cycle at which the first of the instructions is fetched as
clock cycle 1. Assume that if one instruction reads a register during the same clock
cycle as another instruction is writing it, the new value will be read. Do not reorder
the instructions. Instructions are fetched and executed exactly in the order given,
with the pipeline stalling if necessary
(b) Repeat part (a), but now assume that the pipeline does use forwarding.
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