Consider the following sequence of instructions:

add r5, r2, r1

lw r3, 4(r5)

lw r2, 0(r2)

or r3, r5, r3

sw r3, 0(r5)

If there is forwarding, for the first five cycles during the execution of this

code, specify which signals are asserted in each cycle by hazard

detection and forwarding units in the figure given below.

instructio PC memory FID Hazard ID/EX.MemRead detection unit IDEX ontrol EX Registers FMD.Re slerA! FMD AegisterRI I IFAD sterA I FMD.RegisterRd DiEX.AegisterR EX MEM WB ALU Forwarding MEM/WB WB. Data memory