Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data path (IF, D/R, ALU, DM, WB). Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle:

lw $s5, 0($s4) #I1

add $s7, $s5, $s5 #I2

sub $s1, $s5, $s2 #I3

sw $s1, 0($s4) #I4

a. List the read-after-write (current instruction is reading certain registers which haven't been written back yet) data dependencies. As an example, 2 on 1 (r5) shows instruction 2 has data dependency on instruction 1 since it is reading register $s5.

b. Assume the 5-stage MIPS pipeline with no forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer.

c. Assume the 5-stage MIPS pipeline with full forwarding, what is the total number of stall cycles? What is the execution time (in cycles) for the whole program? Sketch a diagram to explain your answer.