Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data path (IF, DIR, ALU, DM, WR). Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle: Sub $t2, $t1, $t3 Add $t4, $t5, $t2 sw $t1, 80 ($t2) Lw $t3, 20 (St4) What is the execution time and the number of stall cycles for forwarding and non forwarding approach? Consider the following sequence of instructions, and assume that it is executed on a 5-stage pipelined data path (IF, DIR, ALU, DM, WR). Also assume that writing into a register happens in the first half of the clock cycle while reading from a register happens in the second half of the clock cycle: Sub $t2, $t1, $t3 Add $t4, $t5, $t2 sw $t1, 80 ($t2) Lw $t3, 20 (St4) What is the execution time and the number of stall cycles for forwarding and non forwarding approach