Consider the following sequence of MIPS instructions: lui $t0,0x4711 ori $t0,$t0,0xACE8 srl $t1,$t0,16 sll $t0,$t0,16 or $t1,$t1,$t0 We have the following options for executing this instruction sequence:

option1: Execute the sequence on our single-cycle datapath that runs at 4 GHz .

option2: Execute the sequence on our multi-cycle datapath that runs at 2.5 GHz.

option3: Execute the sequence on our 5-stage pipelined system that runs at 2.0 GHz and includes a data hazard unit that causes stalls when needed, but does not include a forwarding unit.

c) How many nanoseconds are required to execute the same instruction sequence in the order shown on the pipelined system?