Consider the following sequence of RISC- V instructions: add x15,x12,x11 lwx3,4(x5) lw12,0(x15) or x13,x15,x13 sw x13,0(x15) a) Assume that it is executed on a single cycle processor with clock cycle time 800ps. What is the execution time of the code sequence? b) Assume that it is executed on a 5-stage pipelined processor with clock cycle time 200 ps and without forwarding or hazard detection units. How to ensure correct execution and what is the execution time of the code sequence of yours? c) Assume that it is executed on a 5-stage pipelined processor with clock cycle time 200ps and with forwarding and hazard detection units. How to ensure correct execution and what is the execution time of the code sequence of yours? d) In which case you have got the best performance for your code sequence