Consider the following specifications: Assume the following. - Functional units arenethipelined All stages except EX take one cycle to complete. No limit on reservation stations. - There is no forwarding between functional units. Both integer and floating point results asereqprounigated, through the CDB. - Memory accesses use the integer functional unit to perform effective address calculation. - All loads and stores will access memory during the EX stage, Pipeline stage EX does both the effective address calculation and memory access for loads/stores. - There are unlimited load/store buffers and an infinite instruction queue, - Loads and stores take one cycle to execute and share a memory access unit. - If an instruction is in the WR stage in cycle x, then an instruction that is waiting on the same functional unit (due to a structural hazard) can begin execution in cycle x, unless it needs to read the CDB, in which case it can only start executing on cycle x+1. - Only one instruction can write to the CDB in a clock cycle. Branches and stores do not need the CDB since they dos't have WR stage. - In case there is a conflict for a functional unit or the CDB, assume program order. - When an instruction is done executing in its functional unit and is waiting for the CDB, it is still occupying the functional unit and its reservation station. (hearipg no other instruction may enter). Fill in the execution profile for the code given in the table which includes the cycles that each instruction occupies in the IS, EX, and WR stages and comments to justify your answer such as type of hazards and the registers involved