Question
Consider the following trace of addresses: 1. 0x95E3 2. 0x95E6 3. 0xA63F 4. 0x56EC 5. 0x36BA 6. 0xA63A 7. 0xCAE7 8. 0x56E0 9. 0x2ABA 10.
Consider the following trace of addresses: 1. 0x95E3
2. 0x95E6 3. 0xA63F 4. 0x56EC 5. 0x36BA 6. 0xA63A 7. 0xCAE7 8. 0x56E0 9. 0x2ABA 10. 0x7536 11. 0xD5E8 12. 0xCAB6 13. 0xCAEF 14. 0xA63F 15. 0xEABA 16. 0xE636 17. 0x2AEE 18. 0x0ABC 19. 0xD5E2 20. 0x56B6 21. 0x9537 22. 0x35EA 23. 0x36BC 24. 0x95E9 25. 0x7536 26. 0xCAB7 27. 0xB5E5 28. 0xD5E2 29. 0xEABB 30. 0x15E6
In this question, assume that the cache uses an LRU eviction policy. Please hand-simulate the accesses above in following cache configurations. Indicate which accesses would cause a miss. Indicate when the miss is a compulsory miss. Report the cache miss rate.
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(a) ( C= 7, B =4, S=0)
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(b) ( C= 7, B =4, S=3)
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(c) ( C= 7, B =4, S=1)
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Database And Expert Systems Applications 22nd International Conference Dexa 2011 Toulouse France August/September 2011 Proceedings Part 1 Lncs 6860
Authors: Abdelkader Hameurlain ,Stephen W. Liddle ,Klaus-Dieter Schewe ,Xiaofang Zhou
2011th Edition
3642230873, 978-3642230875
