Consider the ISA of Figure 6.2 and the circuit in Figure 6.9 that implements this ISA. The instruction memory data out bus is delivering an ADD instruction. Imagine that, because of a PCL circuit design error, when decoding an ADD instruction the PCL commands data memory to perform a write operation. In all other respects the PCL correctly commands the processor. Define the totality of ADD instruction behavior that occurs because of the PCL design error.

reg A reg B dst reg unused operation 0 0 0 0 1 add reg A unused dst reg offset operation 0 0 0 1 0 load reg A reg B unused offset operation 0 0 0 1 1 store reg A unused unused offset operation 0 0 1 0 0 jump Figure 62 The binary representation for each of the four instructions listed in Figure 6.1. Each instruction is thirty-two bits long. M1 M3 4 32-bit pgm. ctr. 32-bit adder register unit data in instr. decoder data memory ALU reg A instruction memory M2 addr. in reg B dst reg. addr. in data out data out data in offset operation Figure 6.9 Illustration of data paths including data memory. reg A reg B dst reg unused operation 0 0 0 0 1 add reg A unused dst reg offset operation 0 0 0 1 0 load reg A reg B unused offset operation 0 0 0 1 1 store reg A unused unused offset operation 0 0 1 0 0 jump Figure 62 The binary representation for each of the four instructions listed in Figure 6.1. Each instruction is thirty-two bits long. M1 M3 4 32-bit pgm. ctr. 32-bit adder register unit data in instr. decoder data memory ALU reg A instruction memory M2 addr. in reg B dst reg. addr. in data out data out data in offset operation Figure 6.9 Illustration of data paths including data memory