Consider the MDR of the MIPS hardwired logic architecture for a multi-machine cycle instruction cycle. There are no fixed-point multiplication and division commands. These commands traditionally in the MIPS architecture have as arguments two straight input arguments, while as an output output have the implied double special purpose register hi/lo. For multiplication, output is the double-range result of the operation, while for division, outputs is the quotient (in lo) and the remainder (in hi). The values contained in each section of the hi/lo register are obtained with the help of the mfhi and mflo instructions, which as single argument accept the register where the contents of hi or lo are copied, respectively. If we want to support such commands in the MDR of the MIPS architecture, it is necessary to add a multiply/divide unit to the MDR, with a dual hi/lo register built into it. Consider the new unit with the command mult implements multiplication with a duration of 5 machine cycles, while with the command div implements division with an execution time of 33 machine cycles. In multiplication the lo gets value at the end of 4 th cycle, while in the division lo takes value at the end of it 32nd cycle.

A. Give the schematic diagram of the MDR resulting from the integration of the above multiplication/division module, showing how the new module connects to the existing MDR . Explain any amendments required to the existing MDR. Give a table with all control signals existing, modified existing or new used to support the four new commands and show the additions to the overall architecture state machine for those commands. Minimize the total duration of commands. In particular, mult and div must enter the execution cycles of the corresponding operation, and mfhi and mflo must enter the result storage phase, immediately after the decode phase.

B. Consider the following C code: x = 0; for (i = 0; i < n; i++) x += c[i] ? a[i] * b[i] / c[i] : a[i]; y = x % n; where a, b, c are vectors of 32-bit integers, and i, x, y, n are scalar 32-bit integers variables. If vectors a, b, and c are located in memory with starting addresses contained in registers $s0, $s1, and $s2, respectively, write the corresponding code in MIPS, using only real instructions and no pseudo commands. What is the minimum and what is the maximum number of orders MIPS run by this code? What is the average number of instructions executed by the code if you know that the array c contains zero values with a 10% probability? For each case of maximum, minimum and average number of instructions, how many cycles required to run the code, what percentage of these cycles are consumed in multiplication or division, what is the resulting average CPI, and what is the execution time, if it is done on a 2GHz machine?

C. Now consider a new command multidiv $rs,$rt,$rd which combines the two operations of multiplication and division, so that the division will uses as the divisor the double range result of the multiplication to achieve greater accuracy, but at the expense of the execution time of the division, which it now requires 64 cycles. The multiplication is done between the $rs and $rt registers, while the divisor of the division is taken from the $rd register which to read requires a modification to the 1st reading input of the FC, so that through a suitable multiplexer it is selected rd field of command word instead of rs field. Modify its diagram accordingly MDR of query A, fill in the control signal table with any signals are required, and show the new state machine states to support it new order. Then repeat query B, but using the new muldiv command instead of the classic mult and div, where that makes sense.