Consider the MDR of the wired logic MIPS architecture for an instruction cycle as single as well as multiple machine cycles. Because 16-bit integers and offsets were judged not to meet the needs of applications, a modification to the instruction set architecture was proposed, where integer or offset instructions become two words, with the second containing the integer or offset range of 32 bits, and the first to contain the remaining fields of the command. Without introducing new sub-modules to MDR , please explain if and how you can support the above modification, both in the case of single and in the case of multiple of machine cycles for each instruction cycle, for each of the addi, lw, sw, and beq instructions. More specifically, what plugins do you need in the NED to support these commands? Do you need some new ways of transferring information? You need some new badges control? In the case of multiple machine cycles, give the necessary addition to state machine that describes the execution of instructions with the minimum possible number of clock cycles.