Consider the MDR of the wired logic MIPS architecture for an instruction cycle as single as well as multiple machine cycles. The classic memory addressing supported by the MIPS architecture is the indirect via a shift register.

Now suppose we want to enrich it architecture with the following additional addressing methods:

A. Indirect through scaled register: lwis $rd,($rs,$rt) swiss $rd,($rs,$rt) where the final access address is derived from the sum of its contents register $rs and the contents of register $rt scaled 4 (ie $rt4).

B. Doubly indirect via a shift register: lwd $rt,(off($rs)) swd $rt,(off($rs)) where the last access address is the contents of the addressable memory location which is the sum of the contents of base register $rs plus its extension shift off.

C. Doubly indirect via register with scale index and update: lwdip $rd,(($rs,$rt)) swdip $rd,(($rs,$rt)) where the last access address is the contents of the addressable memory location which is the sum of the contents of the $rs register and the contents of the $rt register scaled by 4 (i.e. $rt4), plus the final access address is stored in $rs.

To support the above commands in MDR MIPS, we are only allowed to extend or introduce multiplexers and connections to the MDR that we studied in the course. So explain if and how you can support them, both in the case of simple and and in the case of multiple machine cycles for each command cycle. More specifically, independently for each command, find if the command can be supported, and if so, what modifications need to be made to the NED on multiplexers and connections, and with what signals these will be used. Modifications should minimize its duration engine cycle in the case of simple, and the number of engine cycles for the involved ones commands in the case of multiple machine cycles. Especially for the second case, it won't the machine cycle time must be increased. In the case of multiple machine cycles, give the necessary addition to state machine that describes the execution of instructions.

Assume that you cannot change its number of read and write ports FC from that of the classic MIPS architecture two read ports and one write port. But you can add options or even multiplexers to address inputs of the FC to get the register numbers from any of the three register fields of the read or write command word. Answer each of the questions A-C independently