Consider the memory hierarchy Given the following information, estimate its average memory latency. Also assume peak main memory bandwidth. Ic and De: L2 cache: Latency= 1 ns, hit ratio= 0.95 (assume the same for both caches) Cache line = 32 B, latency= 3 ns, hit ratio = 0.9 Main memory: 400 MHz SDRAM, 32-bit (4B) data bus Level 1 Block transfer (e.g., 8B) Fastest Memory: Slowest Memory: Level 2 Single-core Processor Processing core DC Ic Cache (SRAMs) Block transfer (e.g., 32B) Main Memory (DRAMS) Page transfer (e.g., 4KB) (X) Non-volatile Memory Hard disk or flash drive 8 (X) Ic: Instruction cache Dc: Data cache (X): Content of memory address X