Consider the merits of the following. In scenario $1$ an add instruction is followed by a load $($or store$)$

instruction that uses the result of the add for its address. For example:

$1.$ R$[0]=$ R$[0]+$ R$[2]$

$2.$ R$[3]=$ Mem$[0+$ R$[0]]$

Scenario $2$ replaces the two instructions with a single instruction of the form:

R$[3]=$ Mem$[0+$ R$[0]+$ R$[2]]$

Note that both scenarios operate on any three registers and for both load or store. You may also assume

that $10\%$ of the load$$store instruction mix from scenario $1$ can be replaced by the single instruction of

scenario $2.$ Let the average frequency of load and store instructions under scenario $1$ be $26\%$ and $9\%$

respectively.

Question: If scenario $2$ increases the duration of the clock period by $5\%$ relative to scenario $1,$ what is

the speedup? $($Assume that the CPI for both systems is equal$)$